| Meno: | Filip |
|---|---|
| Priezvisko: | Koseček |
| Názov: | Acceleration of computations using FPGA |
| Vedúci: | Ing. Duąan Bernát, PhD. |
| Rok: | 2025 |
| Kµúčové slová: | FPGA, processor, instruction, register |
| Abstrakt: | This thesis examines program acceleration techniques leveraging hardware accelerators and their implementations using the FPGA technology. Two approaches were proposed. The first introduced a system consisting of a RISC-V processor coupled with a specialized memory unit capable of writing to multiple memory addresses simultaneously (in one clock cycle). However, the design's spatial complexity prevented us from testing the memory on real applications that require non-trivial memory sizes. The second extends the RISC-V instruction set with custom vector-like capabilities while using the existing processor infrastructure and minimizing the additional FPGA resource usage. Two families of instructions were added to optimize performance of programs which sequentially scan large volumes of data. The first enables searching for a byte value within an array using a single instruction, while the second provides hardware support for counting trailing zeros in a 32-bit register. We demonstrated the effectiveness of the combination of these instruction families by implementing the strlen function using our extensions. Thanks to these enhancements, the execution time was reduced by two-thirds compared to the original unmodified processor executing the library implementation. The thesis also discusses possible applications through various examples, potential improvements, and ideas which could be explored in future research. |
Súbory diplomovej práce:
| kosecek.pdf |
| appendix.zip |
Súbory prezentácie na obhajobe: